[PATCH v3 11/11] soundwire: amd: guard clock-stop register access by acp_rev

[Vijendar Mukunda]

Wrap the readl_poll_timeout and wake-enable writel calls in
amd_sdw_clock_stop() in explicit switch/case blocks on acp_rev
covering ACP63, ACP70, ACP71, and ACP72. An unrecognised revision
now returns -EINVAL rather than silently accessing register offsets
that may not apply to future hardware.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@xxxxxxx>
---
 drivers/soundwire/amd_manager_common.c | 35 ++++++++++++++++++++++----
 1 file changed, 30 insertions(+), 5 deletions(-)

diff --git a/drivers/soundwire/amd_manager_common.c b/drivers/soundwire/amd_manager_common.c
index 4a414fc1b02d..7e3c9176e793 100644
--- a/drivers/soundwire/amd_manager_common.c
+++ b/drivers/soundwire/amd_manager_common.c
@@ -521,7 +521,7 @@ int amd_sdw_manager_start(struct amd_sdw_manager *amd_manager)
  */
 int amd_sdw_clock_stop(struct amd_sdw_manager *amd_manager)
 {
-	u32 val;
+	u32 clk_resume_ctrl, val;
 	int ret;
 
 	ret = sdw_bus_prep_clk_stop(&amd_manager->bus);
@@ -535,16 +535,41 @@ int amd_sdw_clock_stop(struct amd_sdw_manager *amd_manager)
 		return 0;
 	}
 
-	ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val,
-				 (val & AMD_SDW_CLK_STOP_DONE), ACP_DELAY_US, AMD_SDW_TIMEOUT);
+	switch (amd_manager->acp_rev) {
+	case ACP63_PCI_REV_ID:
+	case ACP70_PCI_REV_ID:
+	case ACP71_PCI_REV_ID:
+	case ACP72_PCI_REV_ID:
+		clk_resume_ctrl = ACP_SW_CLK_RESUME_CTRL;
+		break;
+	default:
+		dev_err(amd_manager->dev, "unexpected acp_rev 0x%x\n", amd_manager->acp_rev);
+		return -EINVAL;
+	}
+
+	ret = readl_poll_timeout(amd_manager->mmio + clk_resume_ctrl, val,
+				 (val & AMD_SDW_CLK_STOP_DONE),
+				 ACP_DELAY_US, AMD_SDW_TIMEOUT);
 	if (ret) {
 		dev_err(amd_manager->dev, "SDW%x clock stop failed\n", amd_manager->instance);
 		return 0;
 	}
 
 	amd_manager->clk_stopped = true;
-	if (amd_manager->wake_en_mask)
-		writel(0x01, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance));
+	if (amd_manager->wake_en_mask) {
+		switch (amd_manager->acp_rev) {
+		case ACP63_PCI_REV_ID:
+		case ACP70_PCI_REV_ID:
+		case ACP71_PCI_REV_ID:
+		case ACP72_PCI_REV_ID:
+			writel(0x01, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance));
+			break;
+		default:
+			dev_err(amd_manager->dev, "unexpected acp_rev 0x%x\n",
+				amd_manager->acp_rev);
+			return -EINVAL;
+		}
+	}
 
 	dev_dbg(amd_manager->dev, "SDW%x clock stop successful\n", amd_manager->instance);
 	return 0;
-- 
2.53.0