Re: [PATCH v2] clk: qcom: mmcc-sdm660: enable the parents of the pixel clock sources

[Bjorn Andersson]

On Fri, 02 Oct 2026 13:46:24 -0300, Fabricio Akio wrote:
> pclk0_clk_src and pclk1_clk_src are fed by the DSI PHY PLLs, which
> dsi_pll_14nm_vco_set_rate() resets and only clk_prepare() restarts. The
> DSI host sets the link rates before it prepares the PLL, so the RCG is
> updated against a stopped source, and if it is enabled at that point
> the update times out:
> 
>   pclk0_clk_src: rcg didn't update its configuration.
> 
> [...]

Applied, thanks!

[1/1] clk: qcom: mmcc-sdm660: enable the parents of the pixel clock sources
      commit: 7e24ec7320f5e82f4f2d1809024de19bbee01871

Best regards,
-- 
Bjorn Andersson <andersson@xxxxxxxxxx>