Re: (subset) [PATCH v2 1/4] clk: qcom: ipq-cmn-pll: Correct IPQ8074 NSS NoC rate

[Bjorn Andersson]

On Mon, 26 Oct 2026 13:08:12 +0100, Robert Marko wrote:
> The IPQ8074 NSS NoC bias output feeds the GCC NSS NoC clock without
> a divider.
> 
> GCC and SSDK (Qualcomm vendor switch driver from SDK) both configure that
> clock for 461.5 MHz, while the CMN PLL driver reports its parent at
> 416.5 MHz.
> 
> [...]

Applied, thanks!

[2/4] dt-bindings: clocks: qcom,gcc-ipq8074: Allow CMN PLL bias clocks
      commit: 969f124be6cda13ea890e7330c984c6fdb512753

Best regards,
-- 
Bjorn Andersson <andersson@xxxxxxxxxx>