Re: [PATCH] clk: qcom: camcc-nord: Correct camera clock source tables

[Bjorn Andersson]

On Sun, 27 Sep 2026 00:07:10 +0530, Taniya Das wrote:
> Select the PLL0 odd output for the 200 MHz and 400 MHz CAMNOC RT
> AXI rates.  Use PLL0 main output dividers for the 300 MHz and 400 MHz
> CPHY RX rates.
> 
> CSID and IFE Lite use the CPHY RX rates, so share that table rather
> than duplicating it.  Remove the unsupported 300 MHz CSI PHY timer
> rate.
> 
> [...]

Applied, thanks!

[1/1] clk: qcom: camcc-nord: Correct camera clock source tables
      commit: 3b3328b5c58d92d8025b71cd2e11eda420dd0ad2

Best regards,
-- 
Bjorn Andersson <andersson@xxxxxxxxxx>