[PATCH v3 0/2] Improve eMMC performance for the StarFive JHB100 SoC

[Changhuang Liang]

This series implements programmable support for CIT, allowing host drivers to
set the Send Status Command Idle Timer (CIT) in CQHCI_SSC1, either in
nanoseconds or directly in internal timer clock cycles.
Different platforms can improve MMC performance by configuring their respective
CIT. This series has been tested on the JHB100 SoC.

before:
dd if=/dev/mmcblk0 of=/dev/null bs=1M count=800
838860800 bytes (839 MB, 800 MiB) copied, 9.38511 s, 89.4 MB/s
dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=800
838860800 bytes (839 MB, 800 MiB) copied, 12.2127 s, 68.7 MB/s

after:
dd if=/dev/mmcblk0 of=/dev/null bs=1M count=800
838860800 bytes (839 MB, 800 MiB) copied, 3.19472 s, 263 MB/s
dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=800
838860800 bytes (839 MB, 800 MiB) copied, 10.7587 s, 78.0 MB/s

Changes since v2:

Patch 1:
- cqhci_set_cmd_idle_time() is removed, along with its EXPORT_SYMBOL.
- A new internal helper, cqhci_init_cit(), computes the CIT during
  cqhci_init(), replacing cqhci_itcf_init().
- Replace itcf_hz with a driver-provided cit_ns field.

Patch 2:
- simply assigns cq_host->cit_ns = pltfm_data->cqhci_cit_ns before cqhci_init().
- dropping the post-init cqhci_set_cmd_idle_time() call and its warning path.

v2: https://lore.kernel.org/all/20261104112657.110536-1-changhuang.liang@xxxxxxxxxxxxxxxx/
v1: https://lore.kernel.org/all/20261014121222.31385-1-changhuang.liang@xxxxxxxxxxxxxxxx/

Changhuang Liang (2):
  mmc: cqhci: Add support for setting the Send Status Command Idle Timer
  mmc: sdhci-of-dwcmshc: Set CQHCI command idle time for StarFive JHB100

 drivers/mmc/host/cqhci-core.c       | 45 +++++++++++++++++++++++++++++
 drivers/mmc/host/cqhci.h            | 13 +++++++++
 drivers/mmc/host/sdhci-of-dwcmshc.c |  7 +++++
 3 files changed, 65 insertions(+)

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2.25.1