Re: [PATCH v6 4/8] clk: sunxi-ng: a733: Add PLL clocks support

[Chen-Yu Tsai]

On Sat, Oct 10, 2026 at 12:54 AM Junhui Liu <junhui.liu@xxxxxxxxxxxxx> wrote:
>
> Add PLL clock support for the main CCU of the Allwinner A733 SoC. The
> structure is mostly similar to the sun55i, with the addition of a
> PLL_REF clock that normalizes the hardware-detected DCXO/hosc frequency
> (19.2MHz, 24MHz, or 26MHz) into a consistent 24MHz reference for all
> subsequent PLLs.
>
> Model the independently gated outputs of the peripheral, video, and DE
> PLLs as programmable-divider child clocks, with each output gate modeled
> separately. Follow the documented hierarchy for the derived peripheral
> PLL outputs.
>
> PLL_AUDIO0 uses SDM parameters from the vendor driver to provide a
> 22.5792MHz * 4 output. PLL_AUDIO1 provides fixed /2 and /5 outputs and
> does not expose fractional rates, but its SDM controls are modeled so
> that stale firmware settings can be disabled when an integer rate is
> programmed.
>
> Tested-by: Jerome Brunet <jbrunet@xxxxxxxxxxxx>
> Signed-off-by: Junhui Liu <junhui.liu@xxxxxxxxxxxxx>

Reviewed-by: Chen-Yu Tsai <wens@xxxxxxxxxx>