Re: [PATCH v6 6/8] clk: sunxi-ng: a733: Add mod clocks support

[Chen-Yu Tsai]

On Sat, Oct 10, 2026 at 12:54 AM Junhui Liu <junhui.liu@xxxxxxxxxxxxx> wrote:
>
> Add the module clocks found in the Allwinner A733 SoC, including video,
> storage, interfaces and others. While most of these clocks are similar
> to those in the A523 SoC, this implementation accounts for changes in
> register offsets and introduces support for new modules.
>
> Tested-by: Jerome Brunet <jbrunet@xxxxxxxxxxxx>
> Signed-off-by: Junhui Liu <junhui.liu@xxxxxxxxxxxxx>
> ---
>  drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 1103 ++++++++++++++++++++++++++++++++
>  1 file changed, 1103 insertions(+)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c
> index 371c4297c3ab..7847eec84313 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c

[...]

> +static const struct clk_parent_data dram_parents[] = {
> +       { .hw = &pll_ddr_clk.common.hw, },
> +       { .hw = &pll_periph0_800M_clk.common.hw, },
> +       { .hw = &pll_periph0_600M_clk.hw, },
> +       { .hw = &pll_de_clk.common.hw, },
> +       { .hw = &pll_npu_clk.common.hw, },
> +};
> +static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(dram0_clk, "dram0", dram_parents, 0xc00,
> +                                          0, 4,        /* M */

My LLM agent flagged this: the divider is 5 bits wide, not 4.
Both the user manual (page 149 from start or 128 as numbered on the page)
and the BSP agree.


ChenYu