[PATCH 1/5] dt-bindings: clock: Add STM32MP25 SYSCFG clock controller

[Gabriel Fernandez]

The SYSCFG of the STM32MP23x and STM32MP25x SoCs selects the LTDC pixel
clock among the LTDC kernel clock, the LVDS PHY pixel clock and the DSI
PHY byte lane clock.

Add the binding for this clock controller, described as a
clock-controller sub-node of the SYSCFG node, along with the header
defining the identifiers of the provided clocks.

The inputs are listed in the "ltdc", "lvds", "dsi" order so that the
ones missing on a SoC (no LVDS nor DSI on STM32MP231/233 and
STM32MP251/253) can be omitted at the end of the list. "#clock-cells"
is 1 so that the other clocks of the SYSCFG can be added later without
changing the binding.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@xxxxxxxxxxx>
---
 .../bindings/clock/st,stm32mp25-syscfg-clk.yaml    | 61 ++++++++++++++++++++++
 .../dt-bindings/clock/st,stm32mp25-syscfg-clk.h    | 12 +++++
 2 files changed, 73 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp25-syscfg-clk.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp25-syscfg-clk.yaml
new file mode 100644
index 000000000000..027d14f28b0c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st,stm32mp25-syscfg-clk.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/st,stm32mp25-syscfg-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32MP2 SYSCFG clock controller
+
+maintainers:
+  - Gabriel Fernandez <gabriel.fernandez@xxxxxxxxxxx>
+
+description: |
+  The SYSCFG of the STM32MP23x and STM32MP25x SoCs provides clocks, described
+  by a clock controller sub-node of the SYSCFG node.
+
+  The provided clocks are identified by the macros defined in
+  include/dt-bindings/clock/st,stm32mp25-syscfg-clk.h:
+    - CK_SYSCFG_PIX_LTDC: LTDC pixel clock, selected in the DISPLAYCLKCR
+      register among the LTDC kernel clock, used by the RGB parallel output,
+      the LVDS PHY pixel clock and the DSI PHY byte lane clock.
+
+properties:
+  compatible:
+    const: st,stm32mp25-syscfg-clk
+
+  "#clock-cells":
+    const: 1
+
+  clocks:
+    minItems: 1
+    items:
+      - description: LTDC kernel clock
+      - description: LVDS PHY pixel clock
+      - description: DSI PHY byte lane clock
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: ltdc
+      - const: lvds
+      - const: dsi
+
+required:
+  - compatible
+  - "#clock-cells"
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/st,stm32mp25-rcc.h>
+
+    clock-controller {
+        compatible = "st,stm32mp25-syscfg-clk";
+        #clock-cells = <1>;
+        clocks = <&rcc CK_KER_LTDC>, <&lvds>, <&dsi>;
+        clock-names = "ltdc", "lvds", "dsi";
+    };
+...
diff --git a/include/dt-bindings/clock/st,stm32mp25-syscfg-clk.h b/include/dt-bindings/clock/st,stm32mp25-syscfg-clk.h
new file mode 100644
index 000000000000..74673942898c
--- /dev/null
+++ b/include/dt-bindings/clock/st,stm32mp25-syscfg-clk.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2026 - All Rights Reserved
+ * Author: Gabriel Fernandez <gabriel.fernandez@xxxxxxxxxxx>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_ST_STM32MP25_SYSCFG_CLK_H_
+#define _DT_BINDINGS_CLOCK_ST_STM32MP25_SYSCFG_CLK_H_
+
+#define CK_SYSCFG_PIX_LTDC	0
+
+#endif /* _DT_BINDINGS_CLOCK_ST_STM32MP25_SYSCFG_CLK_H_ */

-- 
2.43.0