[PATCH v2 0/5] clk: stm32: Add the STM32MP2 SYSCFG LTDC pixel clock mux

[Gabriel Fernandez]

On STM32MP23x and STM32MP25x, the LTDC pixel clock is selected in the
SYSCFG DISPLAYCLKCR register among the LTDC kernel clock (RGB output),
the LVDS PHY pixel clock (reset value) and the DSI PHY byte lane clock.
The SYSCFG node is already referenced as the LTDC "ref" clock, but no
driver registers this clock, so the RGB output can't be used.

This series adds a clock driver for this mux. It is based on the RFC
sent by Dario [1] and on the driver delivered in the ST downstream
kernel.

The inputs of the mux can't be described by the "clocks" property of
the SYSCFG node: the SYSCFG is a syscon, whose first clock is taken as
the clock of its registers and enabled around each register access. So
the mux is described by a clock-controller sub-node of the SYSCFG node,
populated by the STM32MP2 SYSCFG driver:
- the mux parents are taken from its "clocks" property, so the inputs
  which don't exist on a SoC (no LVDS/DSI on STM32MP231/233 and
  STM32MP251/253) are simply omitted,
- it uses "#clock-cells = <1>" with a onecell provider, so the other
  clock selections of the SYSCFG can be added later without changing
  the binding.

The SoC devicetrees now use the clock-controller sub-node as the LTDC
"ref" clock instead of the SYSCFG node, whose "#clock-cells" property
is deprecated. Since no driver ever registered a clock on the SYSCFG
node, there is no functional change for existing devicetrees.

Changes compared to the RFC [1]:
- clock-controller sub-node populated by the SYSCFG driver instead of
  an auxiliary device (RFC patch 3/4 dropped)
- parents described by clocks/clock-names instead of global names
- onecell provider and dt-bindings header for the SYSCFG clocks
- SoC devicetrees updated, Engicam board patches dropped

[1] https://lore.kernel.org/all/20261028135915.2665857-1-dario.binacchi@xxxxxxxxxxxxxxxxxxxx/

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@xxxxxxxxxxx>
---
Changes in v2:
- Deprecate the '#clock-cells' property of the SYSCFG node and remove it
  from the SoC devicetrees, the clock-controller sub-node being the only
  provider of the LTDC pixel clock (Sashiko)
- Explain why the mux needs a sub-node: its inputs can't be described by
  the "clocks" property of the SYSCFG node, which is a syscon (Sashiko)
- Link to v1: https://lore.kernel.org/r/20261110-ups_mp25_clk_syscfg-v1-0-667829cd290a@xxxxxxxxxxx

---
Gabriel Fernandez (5):
      dt-bindings: clock: Add STM32MP25 SYSCFG clock controller
      dt-bindings: arm: stm32: Add clock-controller sub-node to STM32MP2 SYSCFG
      clk: stm32: Add STM32MP25 SYSCFG clock driver
      arm64: dts: st: add LTDC pixel clock controller on stm32mp23
      arm64: dts: st: add LTDC pixel clock controller on stm32mp25

 .../bindings/arm/stm32/st,stm32-syscon.yaml        |  11 +-
 .../bindings/clock/st,stm32mp25-syscfg-clk.yaml    |  61 ++++++++++
 arch/arm64/boot/dts/st/stm32mp231.dtsi             |   9 +-
 arch/arm64/boot/dts/st/stm32mp235.dtsi             |   8 +-
 arch/arm64/boot/dts/st/stm32mp251.dtsi             |   9 +-
 arch/arm64/boot/dts/st/stm32mp255.dtsi             |   8 +-
 drivers/clk/stm32/Kconfig                          |  11 ++
 drivers/clk/stm32/Makefile                         |   1 +
 drivers/clk/stm32/clk-stm32mp25-syscfg.c           | 134 +++++++++++++++++++++
 .../dt-bindings/clock/st,stm32mp25-syscfg-clk.h    |  12 ++
 10 files changed, 259 insertions(+), 5 deletions(-)
---
base-commit: 630059a5a632377b9b7b487baccde92b7ae1dd47
change-id: 20261103-ups_mp25_clk_syscfg-6a4224156431

Best regards,
-- 
Gabriel Fernandez <gabriel.fernandez@xxxxxxxxxxx>