Re: [PATCH] phy: freescale: phy-fsl-imx8-mipi-dphy: Fix hs_zero underflow

[Frank Li]

On Tue, Nov 10, 2026 at 02:05:46PM +0200, Stefan Ghetu wrote:
> From: "Oliver F. Brown" <oliver.brown@xxxxxxxxxxx>
>
> The hs_zero timing is computed as
>
> 	n = (144 * (hs_clk_rate / 1000000) - 47500) / 10000;
> 	cfg->m_prg_hs_zero = n < 1 ? 1 : n;
>
> hs_clk_rate is an unsigned long, so the subtraction is done unsigned and
> wraps for any rate below about 330 MHz, where 144 * MHz < 47500. Because
> n is a u32, the wrapped value is never seen as negative and the "n < 1"
> clamp does not take effect. The garbage value is then truncated into the
> 8-bit m_prg_hs_zero register field. At the minimum supported rate of
> 80 MHz this programs 199 on 64-bit and 181 on 32-bit, instead of the
> intended minimum of 1.
>
> Make n signed and do the arithmetic in int so the clamp works on both
> 32-bit and 64-bit. The divided rate is at most 1500, so 144 * 1500 fits
> easily in an int.
>
> Fixes: f4c8116e294b ("phy: Add driver for mixel mipi dphy found on NXP's i.MX8 SoCs")
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Oliver F. Brown <oliver.brown@xxxxxxxxxxx>
> Signed-off-by: Stefan Ghetu <stefan.ghetu@xxxxxxx>
> ---

Reviewed-by: Frank Li <Frank.Li@xxxxxxx>

>  drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
> index 0928a526e2ab..84bd21aaf9e8 100644
> --- a/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
> +++ b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
> @@ -191,8 +191,7 @@ static int mixel_dphy_config_from_opts(struct phy *phy,
>  	unsigned long ref_clk = clk_get_rate(priv->phy_ref_clk);
>  	u32 lp_t, numerator, denominator;
>  	unsigned long long tmp;
> -	u32 n;
> -	int i;
> +	int n, i;
>
>  	if (dphy_opts->hs_clk_rate > DATA_RATE_MAX_SPEED ||
>  	    dphy_opts->hs_clk_rate < DATA_RATE_MIN_SPEED)
> @@ -276,7 +275,7 @@ static int mixel_dphy_config_from_opts(struct phy *phy,
>  	cfg->mc_prg_hs_prepare = dphy_opts->clk_prepare > lp_t ? 1 : 0;
>
>  	/* hs_zero: formula from NXP BSP */
> -	n = (144 * (dphy_opts->hs_clk_rate / 1000000) - 47500) / 10000;
> +	n = (144 * (int)(dphy_opts->hs_clk_rate / 1000000) - 47500) / 10000;
>  	cfg->m_prg_hs_zero = n < 1 ? 1 : n;
>
>  	/* clk_zero: formula from NXP BSP */
> --
> 2.34.1
>
>