Re: [PATCH v2 3/3] MIPS: CI20: Enable SMP with two CPUs

[Paul Cercueil]

Le lundi 09 novembre 2026 à 20:31 -0800, Florian Fainelli a écrit :
> From: 周琰杰 (Zhou Yanjie) <zhouyanjie@xxxxxxxxxxxxxx>
> 
> Enable both JZ4780 cores now that the generic Ingenic platform provides
> secondary CPU reset and mailbox support. The existing device tree
> already reserves TCU channels for both per-CPU clock events.
> 
> Link: https://lists.openwall.net/linux-kernel/2020/05/19/739
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@xxxxxxxxxxxxxx>
> Signed-off-by: Florian Fainelli <f.fainelli@xxxxxxxxx>

Reviewed-by: Paul Cercueil <paul@xxxxxxxxxxxxxxx>

Cheers,
-Paul

> ---
>  arch/mips/configs/ci20_defconfig | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/mips/configs/ci20_defconfig
> b/arch/mips/configs/ci20_defconfig
> index 90536cab417e..09d65094b1bd 100644
> --- a/arch/mips/configs/ci20_defconfig
> +++ b/arch/mips/configs/ci20_defconfig
> @@ -22,6 +22,8 @@ CONFIG_EXPERT=y
>  CONFIG_MACH_INGENIC_SOC=y
>  CONFIG_JZ4780_CI20=y
>  CONFIG_HIGHMEM=y
> +CONFIG_SMP=y
> +CONFIG_NR_CPUS=2
>  CONFIG_HZ_100=y
>  # CONFIG_SUSPEND is not set
>  # CONFIG_SECCOMP is not set