Re: [PATCH net-next v4 4/8] dt-bindings: mfd: Add SoC-e SWIP parent

From: Vasilij Strassheim

Date: Tue Nov 10 2026 - 11:17:33 EST


On Fri, 2026-11-06 at 22:51 +0100, Vasilij Strassheim wrote:
> On Fri, 2026-11-06 at 12:13 +0100, Krzysztof Kozlowski wrote:
> > On Thu, Nov 05, 2026 at 03:16:48PM +0100, Vasilij Strassheim wrote:
> > > Add a binding for the SoC-e SWIP multifunction FPGA IP core.
> > >
> > > Describe the shared MMIO address space and address translation for
> > > the required Ethernet switch child and the optional integrated MDIO
> > > controller and MMIO-controlled MDIO multiplexer.
> > >
> > > Signed-off-by: Vasilij Strassheim <v.strassheim@xxxxxxxxxxxxx>
> > > ---
> > > .../devicetree/bindings/mfd/soce,swip.yaml | 137 +++++++++++++++++++++
> > > 1 file changed, 137 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/mfd/soce,swip.yaml b/Documentation/devicetree/bindings/mfd/soce,swip.yaml
> > > new file mode 100644
> > > index 000000000000..625be299e262
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/mfd/soce,swip.yaml
> > > @@ -0,0 +1,137 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/mfd/soce,swip.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: SoC-e SWIP multifunction Ethernet switch FPGA IP core
> > > +
> > > +maintainers:
> > > + - Vasilij Strassheim <v.strassheim@xxxxxxxxxxxxx>
> > > +
> > > +description:
> > > + SoC-e Switch IP (SWIP) cores integrate Ethernet switching logic, an
> > > + MDIO controller, and an MDIO bus multiplexer in one memory-mapped device.
> > > + The MDIO bus multiplexer is wired to the integrated MDIO controller.
> > > +
> > > +properties:
> > > + compatible:
> > > + const: soce,swip
> > > +
> > > + reg:
> > > + maxItems: 1
> > > +
> > > + '#address-cells':
> > > + const: 1
> > > +
> > > + '#size-cells':
> > > + const: 1
> > > +
> > > + ranges: true
> > > +
> > > + mdio@204:
> > > + $ref: /schemas/net/soce,swip-mdio.yaml#
> > > + unevaluatedProperties: false
> > > +
> > > + mdio-mux@202:
> > > + $ref: /schemas/net/mdio-mux-mmioreg.yaml#
> > > + unevaluatedProperties: false
> > > +
> > > + ethernet-switch:
> >
> > Why are you mixing children with and without bus addresses? This is
> > discouraged and shows that device is not correctly represented, e.g. if
> > the ethernet-switch does not have resources, then THIS device is the
> > ethernet switch.
> >
>
> There is no hardware reason for leaving the switch child unaddressed.
> Just an error that occurred while converting the binding to the MFD
> model.
> I will describe the switch function as an ethernet-switch@0 child node
> with a reg property for it's register resources, like the ocelot MFD
> binding.

It looks like I need a different name for the MFD parent to avoid a
naming collision with the ethernet-switch@0 child. I checked other
bindings but could not find a suitable example.

I would appreciate any suggestions for a suitable name for the parent
node representing the FPGA IP core. It mainly acts as a container for
its child devices. I am considering "bus", "ip-core" or "shell".

> > > + $ref: /schemas/net/dsa/soce,swip-switch.yaml#
> > > + unevaluatedProperties: false
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - '#address-cells'
> > > + - '#size-cells'
> > > + - ranges
> > > + - ethernet-switch
> > > +
> > > +dependentRequired:
> > > + mdio-mux@202:
> > > + - mdio@204
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + ethernet-switch@80020000 {
> > > + compatible = "soce,swip";
> > > + reg = <0x80020000 0x10000>;
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + ranges = <0x0 0x80020000 0x10000>;
> > > +
> > > + mdio_parent: mdio@204 {
> > > + compatible = "soce,swip-mdio";
> > > + reg = <0x204 0xc>, <0x200 0x2>;
> > > + reg-names = "data", "control";
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + };
> > > +
> > > + mdio-mux@202 {
>