Re: [PATCH] spi: sunplus-sp7021: fix clock prepare leak in system sleep suspend

[Mark Brown]

> sp7021_spi_controller_resume() enables the controller clock with
> clk_prepare_enable(), but the matching suspend callback
> sp7021_spi_controller_suspend() only asserts the reset line and never
> disables/unprepares the clock.  Every system sleep suspend/resume cycle
> therefore leaks one clock prepare/enable reference, leaving the clock
> usage count permanently unbalanced.
> 
> Add the missing clk_disable_unprepare() to the suspend callback, in
> reverse order of the resume sequence.

> @@ -508,6 +508,8 @@ static int sp7021_spi_controller_suspend(struct device *dev)
>  	struct spi_controller *ctlr = dev_get_drvdata(dev);
>  	struct sp7021_spi_ctlr *pspim = spi_controller_get_devdata(ctlr);
>  
> +	clk_disable_unprepare(pspim->spi_clk);
> +

This does mean that we're stopping the clock for the first time, I do
hope this won't unconver other bugs...  Most likely not given that we
also reset the IP.

>  	return reset_control_assert(pspim->rstc);
>  }

We stop the clock with the IP out of reset, it might be safer to not
have the IP live with the clock running - that's the order used in
probe().  It's probably better to reorder things in resume rather than
preserve the order there.

-- 
Mark Brown <broonie@xxxxxxxxxx>