Re: [PATCH v2 0/3] MIPS: CI20: Enable SMP with two CPUs

[Florian Fainelli]

On 11/10/26 07:44, Paul Cercueil wrote:
> Hi Florian,
>
> Le lundi 09 novembre 2026 à 20:31 -0800, Florian Fainelli a écrit :
> > This patch series resurrects SMP support for the CI20 board. This was
> > submitted back in 2020 by Zhou Yanjie.
> >
> > Changes in v2:
> >
> > • Moved SMP sources to arch/mips/ingenic/ and the header to
> > arch/mips/include/asm/
> > • Removed CONFIG_MIPS_INGENIC_SMP, using CONFIG_MACH_JZ4780 and CONFIG_SMP
> > directly
> > • Renamed JZ4780-specific SMP symbols to XBurst names
> > • Changed CPU enumeration to assign consecutive logical IDs and removed the
> > explicit two-core limit
> > • Changed mailbox IRQ allocation failure from panic to logging and returning
> > • Shortened commit descriptions, removed Codex attribution, and adjusted
> > source credits and sign-offs
> > • Kept the clock polling patch and CI20 defconfig changes unchanged,
> >    added Paul's R-b for patch #1
> > • Updated the kernel baseline to include additional upstream fixes
>
> You should also have a changelog per-patch, in each patch's header.

This seems to vary on per-subsystem basis, for netdev where I contribute 
the vast majority of the time, putting the changelog in the cover letter 
works, but I will do it on a per-patch basis next time.

> Your patch [1/3] has a Fixes: tag but does not Cc stable@xxxxxxxxxxxxxxx, so
> you'll have to send a v3.
>
> I reviewed [2/3] and it looks good to me, but I'm a bit concerned about
> Nikolaus' reported issue.
>
> Thomas, if you can wait a few days, I can test it on my CI20 and if it works
> report back with a Tested-by: tag.

Thanks Paul, yes please do test it because I could not reproduce what 
Nikolaus reported, that makes me think there must be additional 
configuration options and/or patches being carried that could be 
responsible.
--
Florian