Re: [PATCH v3 1/2] dt-bindings: serial: 8250: add Microchip Core16550

[Conor Dooley]

On Tue, Nov 10, 2026 at 09:06:48AM +1100, Kohei Otsuka via B4 Relay wrote:
> From: Kohei Otsuka <kohei@xxxxxxxxxxxxxxxxx>
> 
> Core16550 is a 16550-compatible UART soft IP core for Microchip FPGAs,
> including the fabric of PolarFire SoC. Its registers follow the 16550A,
> but it raises no interrupt on TEMT. A driver that knows only ns16550a
> waits for one in software RS-485 mode (em485), so RTS stays asserted
> after the first frame and the port stops receiving. ns16550a is
> therefore not a valid fallback.
> 
> Add microchip,core16550-rtl-v3 as a compatible of its own. As for
> Microchip's other FPGA fabric cores, the -rtl-v3 suffix is the major
> RTL version of the IP, Core16550 3.x.
> 
> Link: https://github.com/linux4microchip/meta-mchp/issues/5
> Signed-off-by: Kohei Otsuka <kohei@xxxxxxxxxxxxxxxxx>

With both dt-binding maintainer and microchip fpga hats on:
Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
pw-bot: not-applicable

Thanks,
Conor.

> ---
>  Documentation/devicetree/bindings/serial/8250.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
> index 50d5c977afa3..d9ee14f7b694 100644
> --- a/Documentation/devicetree/bindings/serial/8250.yaml
> +++ b/Documentation/devicetree/bindings/serial/8250.yaml
> @@ -111,6 +111,7 @@ properties:
>            - aspeed,ast2400-vuart
>            - aspeed,ast2500-vuart
>            - intel,xscale-uart
> +          - microchip,core16550-rtl-v3
>            - mrvl,pxa-uart
>            - nuvoton,npcm750-uart
>            - nuvoton,wpcm450-uart
> 
> -- 
> 2.53.0
> 
> 
>

Attachment: signature.asc
Description: PGP signature