Re: [PATCH] i2c: designware: Release slave SCL hold in __i2c_dw_disable()

[Atif Ashhar]

Hi Mika,

On Mon, Nov 09, 2026 at 11:20:06AM +0100, Mika Westerberg wrote:
> > +	if (tx_hold) {
> > +		regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy);
> > +		regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy);
> > +		regmap_write(dev->map, DW_IC_DATA_CMD, 0xFF);
> 
> I'm not super familiar with the slave mode so adding Heikki just in case.
> Can this cause some unintended traffic on the bus towards the master?

No, it cannot initiate new traffic. DW_IC_STATUS_SLAVE_HOLD_TX_FIFO_EMPTY
is only asserted when an external master has already addressed this
controller and initiated a read transfer, and the slave hardware is
actively stretching SCL low waiting for TX data. When no slave read
hold is active, i2c_dw_release_slave_hold() returns early without
writing to DW_IC_DATA_CMD.

Writing 0xff simply satisfies the ongoing master-clocked read byte
while keeping SDA passively high (released via pull-ups), allowing the
external master to finish clocking the byte and terminate the transfer
with NACK/STOP instead of hanging the bus indefinitely.

> Also use 0xff instead.

Ack, I will update 0xFF to 0xff (and wait to see if Heikki has any
comments before sending v2).

Thanks,
Atif