Re: [PATCH v11 2/5] riscv_cbqri: resctrl: Add cache allocation via capacity block mask

[Drew Fustini]

On Sun, Nov 08, 2026 at 03:20:51PM -0800, Drew Fustini wrote:
> Wire CBQRI capacity controllers into resctrl as the L2 and L3 cache
> resources.
> 
> resctrl exposes a single capacity mask per resource, so when more than
> one capacity controller backs a cache level they must report the same
> number of capacity blocks. The same holds for the other capabilities
> resctrl exposes once per resource. A level whose controllers disagree
> is left unexposed. Other levels are unaffected.
> 
> The set of controllers backing each level is fixed when resctrl is set
> up at late_initcall. Control domains are created in the cpuhp online
> callback and keyed on the onlining CPU's cache id from cacheinfo, so a
> CPU that is offline at probe time still joins its domain once it comes
> online, provided a controller for its cache is in that set.
> 
> A CPU whose cache has no controller, or whose domain cannot be created,
> still comes online. It is left out of that level and a warning is
> logged, since bringing the CPU up matters more than controlling its
> cache traffic. A domain is published on the ctrl_domains RCU list only
> after it is fully initialized and brought online, and removed from the
> list before it is taken offline, following the documented safe
> traversal rules.
> 
> Tested-by: Chen Pei <cp0613@xxxxxxxxxxxxxxxxx>
> Acked-by: Reinette Chatre <reinette.chatre@xxxxxxxxx>

Hi Reinette, I still need to get more reviews on this series, but I
wanted to check if your expectation is that all the patches in this
series should be merged through arch/riscv?

Thanks,
Drew