Re: [PATCH v2 2/3] irqchip/ath79-cpu: flush every write buffer of a shared interrupt

[Thomas Gleixner]

On Sun, Nov 08 2026 at 13:57, Rosen Penev wrote:
>  /*
> - * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
> - * these devices typically allocate coherent DMA memory, however the
> - * DMA controller may still have some unsynchronized data in the FIFO.
> - * Issue a flush in the handlers to ensure that the driver sees
> - * the update.
> + * The MIPS core has 8 interrupt lines: IP0/IP1 are software interrupts,
> + * IP7 is the CP0 timer, and IP2-IP6 are wired by the SoC to its devices.
> + * The wiring is fixed in hardware. Several devices can share a line, like
> + * the WMAC and the PCIe root complex on IP2 of AR934x, and their drivers
> + * then request the interrupt with IRQF_SHARED.
>   *
> - * This array map the interrupt lines to the DDR write buffer channels.
> + * Each DMA master writes to DDR through its own write buffer in the DDR
> + * controller, and each write buffer has its own flush register. When a
> + * device raises its interrupt, its last DMA writes may still sit in its
> + * write buffer, so the handler could read stale descriptors or data.
> + *
> + * The CPU interrupt says nothing about which device on a shared line
> + * raised it. So before running the handlers of a line, flush the write
> + * buffers of every device wired to it. Each handler then sees its
> + * device's data, checks its own status, and returns IRQ_NONE if it was
> + * not the source.
> + *
> + * irq_wb_chans maps each CPU interrupt line to the mask of the write
> + * buffer channels to flush, from the qca,ddr-wb-channel-interrupts and
> + * qca,ddr-wb-channels properties.

Thanks for writing this up. That really makes reasoning about this way
more palatable.