Re: [PATCH v6 v6 8/9] ASoC: qcom: lpass-tx-macro: Add support for Bolero v4.0

[Mark Brown]

> Hawi integrates the Bolero v4.0 TX macro. This version extends the
> existing TX macro register layout with CFG2 port-select registers,
> per-path CFG2 registers and an ADPT control block.

> +#define CDC_ADPT0_ADPT_CTRL		(0x0800)
> +#define CDC_TX_ADPT_CTRL_EN_MASK	GENMASK(7, 0)

This is also 8 bits wide.

> +	SND_SOC_DAPM_MUX("TX WSA MUX0", SND_SOC_NOPM, 0, 0, &tx_wsa_mux0_mux),
> +	SND_SOC_DAPM_MUX("TX WSA MUX1", SND_SOC_NOPM, 0, 0, &tx_wsa_mux1_mux),
> +	SND_SOC_DAPM_MUX("TX WSA MUX2", SND_SOC_NOPM, 0, 0, &tx_wsa_mux2_mux),
> +	SND_SOC_DAPM_MUX("TX WSA MUX3", SND_SOC_NOPM, 0, 0, &tx_wsa_mux3_mux),
> +	SND_SOC_DAPM_MUX("TX WSA MUX4", SND_SOC_NOPM, 0, 0, &tx_wsa_mux4_mux),
> +	SND_SOC_DAPM_MUX("TX WSA MUX5", SND_SOC_NOPM, 0, 0, &tx_wsa_mux5_mux),
> +	SND_SOC_DAPM_MUX("TX WSA MUX6", SND_SOC_NOPM, 0, 0, &tx_wsa_mux6_mux),
> +	SND_SOC_DAPM_MUX("TX WSA MUX7", SND_SOC_NOPM, 0, 0, &tx_wsa_mux7_mux),
> +
> +	SND_SOC_DAPM_MUX("TX PORT SEL MUX0", SND_SOC_NOPM, 0, 0, &tx_psel_mux0_mux),
> +	SND_SOC_DAPM_MUX("TX PORT SEL MUX1", SND_SOC_NOPM, 0, 0, &tx_psel_mux1_mux),
> +	SND_SOC_DAPM_MUX("TX PORT SEL MUX2", SND_SOC_NOPM, 0, 0, &tx_psel_mux2_mux),
> +	SND_SOC_DAPM_MUX("TX PORT SEL MUX3", SND_SOC_NOPM, 0, 0, &tx_psel_mux3_mux),
> +	SND_SOC_DAPM_MUX("TX PORT SEL MUX4", SND_SOC_NOPM, 0, 0, &tx_psel_mux4_mux),
> +	SND_SOC_DAPM_MUX("TX PORT SEL MUX5", SND_SOC_NOPM, 0, 0, &tx_psel_mux5_mux),
> +	SND_SOC_DAPM_MUX("TX PORT SEL MUX6", SND_SOC_NOPM, 0, 0, &tx_psel_mux6_mux),
> +	SND_SOC_DAPM_MUX("TX PORT SEL MUX7", SND_SOC_NOPM, 0, 0, &tx_psel_mux7_mux),

> +	{"TX SMIC MUX0", NULL, "TX_SWR_CLK"},
> +	{"TX SMIC MUX0", "SWR_MIC0", "TX WSA MUX0"},
> +	{"TX SMIC MUX0", "SWR_MIC1", "TX WSA MUX0"},
> +	{"TX SMIC MUX0", "SWR_MIC2", "TX WSA MUX0"},
> +	{"TX SMIC MUX0", "SWR_MIC3", "TX WSA MUX0"},
> +	{"TX SMIC MUX0", "SWR_MIC4", "TX WSA MUX0"},
> +	{"TX SMIC MUX0", "SWR_MIC5", "TX WSA MUX0"},
> +	{"TX SMIC MUX0", "SWR_MIC6", "TX WSA MUX0"},
> +	{"TX SMIC MUX0", "SWR_MIC7", "TX WSA MUX0"},
> +	{"TX WSA MUX0", "NO_WSA", "TX PORT SEL MUX0"},
> +	{"TX WSA MUX0", "WSA1",   "TX PORT SEL MUX0"},
> +	{"TX WSA MUX0", "WSA2",   "TX PORT SEL MUX0"},
> +	{"TX WSA MUX0", "WSA3",   "TX PORT SEL MUX0"},
> +	{"TX WSA MUX0", "WSA4",   "TX PORT SEL MUX0"},
> +	{"TX PORT SEL MUX0", "PORT0", "TX SWR_INPUT"},
> +	{"TX PORT SEL MUX0", "PORT1", "TX SWR_INPUT"},
> +	{"TX PORT SEL MUX0", "PORT2", "TX SWR_INPUT"},
> +	{"TX PORT SEL MUX0", "PORT3", "TX SWR_INPUT"},
> +	{"TX PORT SEL MUX0", "PORT4", "TX SWR_INPUT"},

These muxes look weird, the different settings don't seem to change
anything?

-- 
Mark Brown <broonie@xxxxxxxxxx>