x86 VERW clarification required from AMD

[Christian Ludloff]

With AMD SB-7029 refreshed by AMD SB-7073
and with AMD SB-3055 out as well, the updated
AMD TSA doc [1] continues to state that...

  "Execution of VERW at non-CPL0 will not clear
  the relevant microarchitectural data structures."

Intel doesn't seem to document such a limitation
for VERW. Can AMD please spell out how CPL3
code can transition between trusted vs untrusted
without a roundtrip through the OS or HV?

Also, if VERW is CPL-dependent, then so should
its CPUID flag, ext.21h.EAX[5], be... right?

Thanks in advance for the required clarifications!

[1] https://www.amd.com/content/dam/amd/en/documents/resources/bulletin/technical-guidance-for-mitigating-transient-scheduler-attacks.pdf

PS: That doc tries to portray 3055 as theoretical,
which it is not. Please get patched... asap.

--
C.