[PATCH 4/6] dt-bindings: memory: tegra: Add Tegra114 EMC channel registers

From: Patrick Fischer via B4 Relay

Date: Wed Nov 11 2026 - 05:14:40 EST


From: Patrick Fischer <admin@xxxxxxxxxxxxxxxxxx>

The Tegra114 EMC has two channels of 32 bits. Besides the register
block that writes to both channels, each channel has its own block,
EMC0 at 0x7001a000 and EMC1 at 0x7001a800 (Tegra 4 TRM address map).

Some settings have to differ between the channels: for pad
auto-calibration, channel 0 is the master and channel 1 is the slave
(EMC_AUTO_CAL_CONFIG bit 27, AUTO_CAL_SLAVE_MODE), which cannot be
programmed through the broadcast block. Allow the two channel blocks as
second and third reg entries for Tegra114: a device tree has either
only the broadcast block, as the existing ones do, or all three. The
meaning follows from the position, so no reg-names are needed. Tegra124
keeps a single entry.

Signed-off-by: Patrick Fischer <admin@xxxxxxxxxxxxxxxxxx>
---
.../bindings/memory-controllers/nvidia,tegra124-emc.yaml | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml
index 8e0c67d671f9..c9335483ba85 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml
@@ -25,7 +25,13 @@ properties:
- const: nvidia,tegra124-emc

reg:
- maxItems: 1
+ oneOf:
+ - items:
+ - description: EMC registers, writes go to all channels
+ - items:
+ - description: EMC registers, writes go to all channels
+ - description: EMC channel 0 registers
+ - description: EMC channel 1 registers

clocks:
items:
@@ -218,6 +224,9 @@ allOf:
enum:
- nvidia,tegra124-emc
then:
+ properties:
+ reg:
+ maxItems: 1
patternProperties:
"^emc-timings-[0-9]+$":
patternProperties:

--
2.56.0