Re: [PATCH v25 00/11] Add Renesas RZ/G3L SD/eMMC support

[Ulf Hansson]

On Wed, Oct 28, 2026 at 1:51 PM Biju Das <biju.das.au@xxxxxxxxx> wrote:
>
> Hi All,
>
> The Renesas RZ/G3L SoC has:
>
> Channel 0 supports SD and eMMC (including HS400/HS400ES).
> Channel 1 supports SD and eMMC (except for HS400).
> Channel 2 supports SD.
>
> The SoC supports a maximum frequency of 150 MHz. The SD0 interface does
> not support IOVS and PWEN in the SDHI register (no internal regulator),
> unlike SD1 and SD2. It has an internal divider for all modes except HS400.
> It also has a 2048-bit divider compared to 512 on others. Moreover
> RZ/G3L supports HS400 enhanced strobe mode.
>
> This patch series support all modes except HS400. HS400 support will be
> added later.
>
> This patch series tested on smarc-rz{v2l,g2l,g2lc,g2ul,g3s,g3l,g3e},
> rz{v2h,t2h}-evk and hihope-rz{g2h,g2m,g2n} boards
>
> v24->v25:
>  * Added max-frequency is a required property for SoCs with internal
>    divider.
>  * Retained the tags as the change is trivial.
>  * Restored struct of_default_cfg.
>  * Updated commit description for patch#3,#4,#6,#10 and #11
>  * Dropped initializing clk_mask as it uses the default value.
>  * Added suffix ULL to macro SDHI_CLK_MASK_DEFAULT.
>  * Fixed a very low or zero clock rate from the clock provider that causes
>    an infinite loop in `renesas_sdhi_set_clock` by max operator.
>  * Restored the data type of max_divider from signed int to unsigned int.
>  * Dropped initializing max_divider as it use default value.
>  * Updated mmc->f_min calculation with clk_round_rate().
>  * Updated the comment using "ilog2(max_divider)" instead of "{9,11}".
>  * Dropped initializing clk_div_mask as it use default value.
>  * Updated renesas_sdhi_set_hw_adjustment_delay() with force_clear
>    parameter
>  * Added a comment in renesas_sdhi_execute_tuning() for tuning delay.
>  * In probe, if the SCC registers are not available, it clear the tuning
>    delay flag.
>  * Dropped default masks from struct of_data_rz_g2l.
>  * Dropped renesas_sdhi_is_internal_divider_enabled().
>  * Added a comment about the internal divider in
>    renesas_sdhi_clk_update() and replaced 'clkh_shift = 1' with
>    'clkh_shift--'
>  * Moved mmc->f_max to probe() and made it fail if max-frequency is
>    not defined in DT for SoCs with an internal divider.
>  * Updated tmio_mmc_host_probe() to set write32_hook() to NULL if
>    TMIO_MMC_HAS_IDLE_WAIT is not defined.
>  * Added macros RZG3L_SDHI_SCC_HWADJ2_{1_8V,3_3V}
>  * Replaced the quirks sdhi_quirks_rzg3l with sdhi_quirks_fixed_addr.
>  * Added helper renesas_sdhi_sclken() to handle 16-bit and 32-bit access.
>  * Updated renesas_sdhi_set_clock() with max_divider check for
>    TMIO_MMC_INTERNAL_DIVIDER instead of SDHI_MAX_DIVIDER_DEFAULT for
>    consistency with tmio_mmc_reset().

The v25 series applied for next, thanks!

[...]

Kind regards
Uffe