Re: [PATCH 1/2] arm64: suspend: Save POR_EL0 over suspend

[Vladimir Murzin]

On 11/5/26 16:05, Mark Brown wrote:
> POR_EL0 is a live EL0 register on systems with S1POE but it is not saved
> and restored by cpu_do_suspend()/cpu_do_resume(). This means that the task
> that initiated suspend can return to userspace with an UNKNOWN value. Fix
> this by saving and restoring the value over suspend.
> 
> This increases the size of struct cpu_suspend_ctx.

This seems to be implied since we need storage to keep register value, no?

> 
> Fixes: bf83dae90fbc ("arm64: enable the Permission Overlay Extension for EL0")
> Signed-off-by: Mark Brown <broonie@xxxxxxxxxx>
> Cc: stable@xxxxxxxxxxxxxxx
> ---
>  arch/arm64/include/asm/suspend.h | 2 +-
>  arch/arm64/mm/proc.S             | 8 ++++++++
>  2 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/include/asm/suspend.h b/arch/arm64/include/asm/suspend.h
> index a5abf0615594..eb9ce315f146 100644
> --- a/arch/arm64/include/asm/suspend.h
> +++ b/arch/arm64/include/asm/suspend.h
> @@ -2,7 +2,7 @@
>  #ifndef __ASM_SUSPEND_H
>  #define __ASM_SUSPEND_H
>  
> -#define NR_CTX_REGS 15
> +#define NR_CTX_REGS 16
>  #define NR_CALLEE_SAVED_REGS 12
>  
>  /*
> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> index b1516630904d..664ea9e3b9ad 100644
> --- a/arch/arm64/mm/proc.S
> +++ b/arch/arm64/mm/proc.S
> @@ -117,6 +117,10 @@ alternative_else_nop_endif
>  alternative_if ARM64_SME
>  	mrs_s	x2, SYS_TPIDR2_EL0
>  	str	x2, [x0, #112]
> +alternative_else_nop_endif
> +alternative_if ARM64_HAS_S1POE
> +	mrs	x2, REG_POR_EL0
> +	str	x2, [x0, #120]
>  alternative_else_nop_endif
>  	ret
>  SYM_FUNC_END(cpu_do_suspend)
> @@ -160,6 +164,10 @@ alternative_if ARM64_SME
>  	ldr	x2, [x0, #112]
>  	msr_s	SYS_TPIDR2_EL0, x2
>  alternative_else_nop_endif
> +alternative_if ARM64_HAS_S1POE
> +	ldr	x2, [x0, #120]
> +	msr	REG_POR_EL0, x2
> +alternative_else_nop_endif
>  
>  	msr	sctlr_el1, x12
>  	set_this_cpu_offset x13
> 
> -- 2.47.3
> 

FWIW,

Reviewed-by: Vladimir Murzin <vladimir.murzin@xxxxxxx>