[PATCH 2/2] dt-bindings: clock: convert zynq-7000.txt to yaml
From: Radhey Shyam Pandey
Date: Wed Nov 11 2026 - 10:14:56 EST
Convert the Zynq 7000 clock controller binding to DT schema format.
ps-clk-frequency becomes optional with a documented 33 MHz default. The
text version listed it as required, but zynq-7000.dtsi does not set it
and five in-tree boards (zynq-cc108 and zynq-zc770-xm010 through xm013)
never override it, so requiring it would reject device trees that are
already in use.
trace_emio_clk is added to the clock inputs. It is the external trace
clock feeding the debug trace mux, which the text version never listed.
The example is corrected the same way: it used can_mio_clk_23, which
does not match the mio_clk_XX form this binding defines for an EMIO
clock on a MIO pin.
clock-output-names is enumerated as 48 const entries instead of the
prose "shall be a list of the outputs below", so the names and their
order are now checked. The clock cell is an index into that list.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxx>
---
.../bindings/clock/xlnx,ps7-clkc.yaml | 145 ++++++++++++++++++
.../devicetree/bindings/clock/zynq-7000.txt | 110 -------------
2 files changed, 145 insertions(+), 110 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/xlnx,ps7-clkc.yaml
delete mode 100644 Documentation/devicetree/bindings/clock/zynq-7000.txt
diff --git a/Documentation/devicetree/bindings/clock/xlnx,ps7-clkc.yaml b/Documentation/devicetree/bindings/clock/xlnx,ps7-clkc.yaml
new file mode 100644
index 000000000000..2d6ce2ba5d87
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/xlnx,ps7-clkc.yaml
@@ -0,0 +1,145 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/xlnx,ps7-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynq 7000 clock controller
+
+maintainers:
+ - Michal Simek <michal.simek@xxxxxxx>
+
+description:
+ The clock controller generates the PS clocks from the three PLLs and the
+ clock generators in the System Level Control Registers (SLCR). It is a
+ child node of the SLCR. See Chapter 25 of the Zynq TRM (UG585) for more
+ information about Zynq clocks.
+
+properties:
+ compatible:
+ const: xlnx,ps7-clkc
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 58
+
+ clock-names:
+ minItems: 1
+ maxItems: 58
+ description:
+ Optional (E)MIO clock sources. mio_clk_XX names the EMIO clock on MIO
+ pin XX and may be given for pins 00 to 53.
+ items:
+ oneOf:
+ - enum: [ gem0_emio_clk, gem1_emio_clk, swdt_ext_clk, trace_emio_clk ]
+ - pattern: '^mio_clk_([0-4][0-9]|5[0-3])$'
+
+ clock-output-names:
+ description:
+ Names for the 48 clock outputs, in the order the single clock cell
+ indexes them.
+ items:
+ - const: armpll
+ - const: ddrpll
+ - const: iopll
+ - const: cpu_6or4x
+ - const: cpu_3or2x
+ - const: cpu_2x
+ - const: cpu_1x
+ - const: ddr2x
+ - const: ddr3x
+ - const: dci
+ - const: lqspi
+ - const: smc
+ - const: pcap
+ - const: gem0
+ - const: gem1
+ - const: fclk0
+ - const: fclk1
+ - const: fclk2
+ - const: fclk3
+ - const: can0
+ - const: can1
+ - const: sdio0
+ - const: sdio1
+ - const: uart0
+ - const: uart1
+ - const: spi0
+ - const: spi1
+ - const: dma
+ - const: usb0_aper
+ - const: usb1_aper
+ - const: gem0_aper
+ - const: gem1_aper
+ - const: sdio0_aper
+ - const: sdio1_aper
+ - const: spi0_aper
+ - const: spi1_aper
+ - const: can0_aper
+ - const: can1_aper
+ - const: i2c0_aper
+ - const: i2c1_aper
+ - const: uart0_aper
+ - const: uart1_aper
+ - const: gpio_aper
+ - const: lqspi_aper
+ - const: smc_aper
+ - const: swdt
+ - const: dbg_trc
+ - const: dbg_apb
+
+ ps-clk-frequency:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 33333333
+ description:
+ Frequency of the oscillator providing ps_clk, in Hz. Zynq platforms
+ usually fit a 33 MHz oscillator.
+
+ fclk-enable:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+ maximum: 0xf
+ description:
+ Bit mask of FCLKs to enable at boot time. Bits 0 to 3 correspond to
+ FCLK0 to FCLK3.
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - clock-output-names
+
+additionalProperties: false
+
+examples:
+ - |
+ clkc: clock-controller@100 {
+ compatible = "xlnx,ps7-clkc";
+ reg = <0x100 0x100>;
+ #clock-cells = <1>;
+ ps-clk-frequency = <33333333>;
+ fclk-enable = <0>;
+ clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
+ "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x",
+ "ddr3x", "dci", "lqspi", "smc", "pcap",
+ "gem0", "gem1", "fclk0", "fclk1", "fclk2",
+ "fclk3", "can0", "can1", "sdio0", "sdio1",
+ "uart0", "uart1", "spi0", "spi1", "dma",
+ "usb0_aper", "usb1_aper", "gem0_aper",
+ "gem1_aper", "sdio0_aper", "sdio1_aper",
+ "spi0_aper", "spi1_aper", "can0_aper",
+ "can1_aper", "i2c0_aper", "i2c1_aper",
+ "uart0_aper", "uart1_aper", "gpio_aper",
+ "lqspi_aper", "smc_aper", "swdt", "dbg_trc",
+ "dbg_apb";
+ clocks = <&clkc 16>, <&clk_foo>;
+ clock-names = "gem1_emio_clk", "mio_clk_23";
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt
deleted file mode 100644
index d93746cf2975..000000000000
--- a/Documentation/devicetree/bindings/clock/zynq-7000.txt
+++ /dev/null
@@ -1,110 +0,0 @@
-Device Tree Clock bindings for the Zynq 7000 EPP
-
-The Zynq EPP has several different clk providers, each with there own bindings.
-The purpose of this document is to document their usage.
-
-See clock_bindings.txt for more information on the generic clock bindings.
-See Chapter 25 of Zynq TRM for more information about Zynq clocks.
-
-== Clock Controller ==
-The clock controller is a logical abstraction of Zynq's clock tree. It reads
-required input clock frequencies from the devicetree and acts as clock provider
-for all clock consumers of PS clocks.
-
-Required properties:
- - #clock-cells : Must be 1
- - compatible : "xlnx,ps7-clkc"
- - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
- - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
- (usually 33 MHz oscillators are used for Zynq platforms)
- - clock-output-names : List of strings used to name the clock outputs. Shall be
- a list of the outputs given below.
-
-Optional properties:
- - clocks : as described in the clock bindings
- - clock-names : as described in the clock bindings
- - fclk-enable : Bit mask to enable FCLKs statically at boot time.
- Bit [0..3] correspond to FCLK0..FCLK3. The corresponding
- FCLK will only be enabled if it is actually running at
- boot time.
-
-Clock inputs:
-The following strings are optional parameters to the 'clock-names' property in
-order to provide an optional (E)MIO clock source.
- - swdt_ext_clk
- - gem0_emio_clk
- - gem1_emio_clk
- - mio_clk_XX # with XX = 00..53
-...
-
-Clock outputs:
- 0: armpll
- 1: ddrpll
- 2: iopll
- 3: cpu_6or4x
- 4: cpu_3or2x
- 5: cpu_2x
- 6: cpu_1x
- 7: ddr2x
- 8: ddr3x
- 9: dci
- 10: lqspi
- 11: smc
- 12: pcap
- 13: gem0
- 14: gem1
- 15: fclk0
- 16: fclk1
- 17: fclk2
- 18: fclk3
- 19: can0
- 20: can1
- 21: sdio0
- 22: sdio1
- 23: uart0
- 24: uart1
- 25: spi0
- 26: spi1
- 27: dma
- 28: usb0_aper
- 29: usb1_aper
- 30: gem0_aper
- 31: gem1_aper
- 32: sdio0_aper
- 33: sdio1_aper
- 34: spi0_aper
- 35: spi1_aper
- 36: can0_aper
- 37: can1_aper
- 38: i2c0_aper
- 39: i2c1_aper
- 40: uart0_aper
- 41: uart1_aper
- 42: gpio_aper
- 43: lqspi_aper
- 44: smc_aper
- 45: swdt
- 46: dbg_trc
- 47: dbg_apb
-
-Example:
- clkc: clkc@100 {
- #clock-cells = <1>;
- compatible = "xlnx,ps7-clkc";
- ps-clk-frequency = <33333333>;
- reg = <0x100 0x100>;
- clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
- "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
- "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
- "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
- "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
- "dma", "usb0_aper", "usb1_aper", "gem0_aper",
- "gem1_aper", "sdio0_aper", "sdio1_aper",
- "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
- "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
- "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
- "dbg_trc", "dbg_apb";
- # optional props
- clocks = <&clkc 16>, <&clk_foo>;
- clock-names = "gem1_emio_clk", "can_mio_clk_23";
- };
--
2.44.4