[tip: irq/drivers] dt-bindings: interrupt-controller: qca,ar7100-cpu-intc: Allow shared write buffer interrupts

[tip-bot2 for Rosen Penev]

The following commit has been merged into the irq/drivers branch of tip:

Commit-ID:     e5d5fe940c1e329f561ea636700672a5bd4a785b
Gitweb:        https://git.kernel.org/tip/e5d5fe940c1e329f561ea636700672a5bd4a785b
Author:        Rosen Penev <rosenp@xxxxxxxxx>
AuthorDate:    Sun, 08 Nov 2026 13:57:36 -08:00
Committer:     Thomas Gleixner <tglx@xxxxxxxxxx>
CommitterDate: Wed, 11 Nov 2026 00:56:19 +01:00

dt-bindings: interrupt-controller: qca,ar7100-cpu-intc: Allow shared write buffer interrupts

On AR934x and QCA953x, the WMAC and the PCIe root complex share CPU
interrupt 2, but write to DDR through different write buffers. Document
that such an interrupt is listed once for each write buffer, and that
all of them are flushed.

Signed-off-by: Rosen Penev <rosenp@xxxxxxxxx>
Signed-off-by: Thomas Gleixner <tglx@xxxxxxxxxx>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxxxxx>
Link: https://patch.msgid.link/20261108215738.113582-2-rosenp@xxxxxxxxx
---
 Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-cpu-intc.yaml | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-cpu-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-cpu-intc.yaml
index ab32a91..becec88 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-cpu-intc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-cpu-intc.yaml
@@ -29,7 +29,10 @@ properties:
     const: 1
 
   qca,ddr-wb-channel-interrupts:
-    description: List of interrupts needing a write buffer flush
+    description:
+      List of interrupts needing a write buffer flush. An interrupt shared by
+      several devices that use different write buffers is listed once for
+      each of them, and all of their write buffers are flushed.
     $ref: /schemas/types.yaml#/definitions/uint32-array
 
   qca,ddr-wb-channels: