Re: [PATCH v4 00/13] Enable USB3 for Qualcomm IPQ5018

[Vinod Koul]

On 20-10-26, 09:59, Konrad Dybcio wrote:
> On 9/8/26 11:40 AM, George Moussalem via B4 Relay wrote:
> > Patch series adds Qualcomm 22ull Super-Speed USB UNIPHY driver support
> > present in Qualcomm IPQ5018 and IPQ5332 SoC which is required to enable
> > USB3. This PHY is interfaced with SNPS DWC3 USB and SNPS DWC PCIe.
> > Either one of the interface can use it via the mux selection present in
> > the TCSR register. Current patch series adds the support for UNIPHY with
> > DWC3 USB.
> > 
> > The series is now split into 3 parts:
> > 1. Flatten USB Controller Nodes on IPQ SoCs
> >    link: https://lore.kernel.org/r/20260906-ipq-flatten-usb-v3-0-13e4e0f63123@xxxxxxxxxxx
> > 2. Enable USB3 for Qualcomm IPQ5018 (this patch series)
> > 3. Enable USB3 for Qualcomm IPQ5332 (to be submitted)
> > 
> > ---
> > Changes in v4:
> 
> [...]
> 
> > - It's worth noting that I left the logic to register 1 phy in this
> >   patch unchanged despite Konard's suggestion to register both
> >   (PCIe and USB3) to avoid changing the existing binding for the
> >   existing PCIe phy instances in ipq5018/ipq5332. Although the silicon
> >   is capable of supporting both PCIe and USB3, the instances in scope
> >   are wired for single mode only. The next patch set will register both
> >   PCIe and USB3 PHYs for the combo PHY instance in IPQ5332 and use
> >   #phy-cells to select the right PHY in the respective PCIe and USB3
> >   controller nodes.
> 
> We need a bindings change either way, so might as well do it
> "right"!

Are we getting an update to binding? Or is this good to be picked?

-- 
~Vinod