Re: [PATCH v2 20/24] spi: zx: Add ZTE ZX family SPI flash controller driver

[Navid Ghahremani]

Hi Stefan,

Thanks for looking at the changes. Since you plan to submit the driver
yourself, I am dropping the SPI patches from my series, so this is just
to answer your questions.

Stefan Dösinger wrote:
> So IOW, this function should primarily configure ZX_QSPI_TIMING_REG. If the
> target clock can't be achieved with the controller input clock (e.g. divider
> is larger than ZX_QSPI_TIMING_REG supports or clock rate is lower than
> requested SPI speed), then a change to the wclk is in order.

Agreed. I only changed the wclk because that is what worked on my
board, and I never checked whether ZX_QSPI_TIMING_REG has a divider.

> > +	ctrl->min_speed_hz = clk_round_rate(qspi->wclk, 1);
> > +	ctrl->max_speed_hz = 50000000;
> This looks wrong - the max speed is probably the highest possible wclk rate,
> the lowest speed the lowest possible wclk rate divided by the highest possible
> divider.

Agreed.

> > +	/* Ensure proper data sampling point */
> > +	reg = readl_relaxed(qspi->io_base + ZX_QSPI_TIMING_REG);
> > +	if (!FIELD_GET(GENMASK(17, 16), reg)) {
> > +		reg |= FIELD_PREP(GENMASK(17, 16), 1);
> > +		writel_relaxed(reg, qspi->io_base + ZX_QSPI_TIMING_REG);
> > +	}
> I don't know what this is doing. Can you elaborate?

That value came over from the earlier driver I used on this board,
which always wrote 1 to bits 17:16. There is no public register
documentation for this SoC, so I kept it, and v2 only writes it when
the field reads 0. The sampling point in the comment is my guess at
what it does and I have not tried other values. If it matters for your
driver, I can try 0 to 3 on my board and tell you which ones read the
flash correctly.

Best regards,
Navid