[PATCH v3 5/6] arm64: dts: qcom: kodiak: use thermal hw-bin trips
From: Gaurav Kohli
Date: Fri Nov 13 2026 - 05:24:33 EST
From: Amit Kucheria <amit.kucheria@xxxxxxxxxxxxxxxx>
kodiak-based SoCs are binned at manufacturing time, with the bin
computed from the jtag-id and feat-id qfprom fuses. The tsens driver
now reads these and feeds the resulting bin to the thermal core, which
selects per-bin trip temperatures.
Add the jtag-id and feat-id nvmem cells to the tsens nodes and convert
the passive mitigation trip points from a fixed 95C to per-bin values
(95C for bin 0x1, 105C for bin 0x2) using the new
temperature-bin/thermal-hw-bin properties.
Signed-off-by: Amit Kucheria <amit.kucheria@xxxxxxxxxxxxxxxx>
Co-developed-by: Gaurav Kohli <gaurav.kohli@xxxxxxxxxxxxxxxx>
Signed-off-by: Gaurav Kohli <gaurav.kohli@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/kodiak.dtsi | 58 +++++++++++++++++++++++++++---------
1 file changed, 44 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 10e9a5279ed6..79553bf43a7a 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -1028,6 +1028,18 @@ gpu_speed_bin: gpu-speed-bin@1e9 {
reg = <0x1e9 0x2>;
bits = <5 8>;
};
+
+ jtag_id: jtag-id@180 {
+ reg = <0x180 0x4>;
+ /* bits = <offset width>: 20 bits at offset 0 */
+ bits = <0 20>;
+ };
+
+ feat_id: feat-id@180 {
+ reg = <0x180 0x4>;
+ /* bits = <offset width>: 8 bits at offset 20 */
+ bits = <20 8>;
+ };
};
sdhc_1: mmc@7c4000 {
@@ -5810,6 +5822,8 @@ tsens0: thermal-sensor@c263000 {
compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
reg = <0 0x0c263000 0 0x1ff>, /* TM */
<0 0x0c222000 0 0x1ff>; /* SROT */
+ nvmem-cells = <&jtag_id>, <&feat_id>;
+ nvmem-cell-names = "jtag-id", "feat-id";
#qcom,sensors = <15>;
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
@@ -5821,6 +5835,8 @@ tsens1: thermal-sensor@c265000 {
compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
reg = <0 0x0c265000 0 0x1ff>, /* TM */
<0 0x0c223000 0 0x1ff>; /* SROT */
+ nvmem-cells = <&jtag_id>, <&feat_id>;
+ nvmem-cell-names = "jtag-id", "feat-id";
#qcom,sensors = <12>;
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
@@ -7164,7 +7180,8 @@ cpu0_alert0: trip-point0 {
};
cpu0_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7207,7 +7224,8 @@ cpu1_alert0: trip-point0 {
};
cpu1_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7250,7 +7268,8 @@ cpu2_alert0: trip-point0 {
};
cpu2_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7293,7 +7312,8 @@ cpu3_alert0: trip-point0 {
};
cpu3_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7336,7 +7356,8 @@ cpu4_alert0: trip-point0 {
};
cpu4_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7379,7 +7400,8 @@ cpu5_alert0: trip-point0 {
};
cpu5_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7422,7 +7444,8 @@ cpu6_alert0: trip-point0 {
};
cpu6_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7465,7 +7488,8 @@ cpu7_alert0: trip-point0 {
};
cpu7_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7508,7 +7532,8 @@ cpu8_alert0: trip-point0 {
};
cpu8_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7551,7 +7576,8 @@ cpu9_alert0: trip-point0 {
};
cpu9_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7594,7 +7620,8 @@ cpu10_alert0: trip-point0 {
};
cpu10_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7637,7 +7664,8 @@ cpu11_alert0: trip-point0 {
};
cpu11_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7752,7 +7780,8 @@ gpuss0-thermal {
trips {
gpuss0_alert0: trip-point0 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
@@ -7779,7 +7808,8 @@ gpuss1-thermal {
trips {
gpuss1_alert0: trip-point0 {
- temperature = <95000>;
+ temperature-bin = <95000>, <105000>;
+ thermal-hw-bin = <0x1>, <0x2>;
hysteresis = <2000>;
type = "passive";
};
--
2.34.1