[PATCH v3 3/3] arm64: dts: rockchip: Add the clock and reset of the RK3588 PCIe SMMU

[Arun Iyengar via B4 Relay]

From: Arun Iyengar <aiyengar1990@xxxxxxxxx>

mmu600_pcie is enabled in rk3588-base.dtsi, but its node lacks its
clock, ACLK_MMU_PCIE. On a board without an enabled PCIe controller
(e.g. the Orange Pi 5 with its M.2 slot in SATA mode) nothing holds the
clock, it is gated as unused, and reboot hangs in
arm_smmu_device_shutdown() until the watchdog fires.

Add the clock, so the SMMU driver keeps it running, and the reset,
SRST_A_MMU_PCIE.

Fixes: da92d3dfc871 ("arm64: dts: rockchip: enable the mmu600_pcie IOMMU on the rk3588 SoC")
Reviewed-by: Sebastian Reichel <sebastian.reichel@xxxxxxxxxxxxx>
Signed-off-by: Arun Iyengar <aiyengar1990@xxxxxxxxx>
---
 arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index aa69fd3793fd..45c1bb335447 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -559,6 +559,8 @@ mmu600_pcie: iommu@fc900000 {
 			     <GIC_SPI 374 IRQ_TYPE_EDGE_RISING 0>,
 			     <GIC_SPI 367 IRQ_TYPE_EDGE_RISING 0>;
 		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+		clocks = <&cru ACLK_MMU_PCIE>;
+		resets = <&cru SRST_A_MMU_PCIE>;
 		#iommu-cells = <1>;
 	};
 

-- 
2.55.0