Re: [PATCH] phy: freescale: phy-fsl-imx8-mipi-dphy: Fix hs_zero underflow

[Vinod Koul]

On Tue, 10 Nov 2026 14:05:46 +0200, Stefan Ghetu wrote:
> The hs_zero timing is computed as
> 
> 	n = (144 * (hs_clk_rate / 1000000) - 47500) / 10000;
> 	cfg->m_prg_hs_zero = n < 1 ? 1 : n;
> 
> hs_clk_rate is an unsigned long, so the subtraction is done unsigned and
> wraps for any rate below about 330 MHz, where 144 * MHz < 47500. Because
> n is a u32, the wrapped value is never seen as negative and the "n < 1"
> clamp does not take effect. The garbage value is then truncated into the
> 8-bit m_prg_hs_zero register field. At the minimum supported rate of
> 80 MHz this programs 199 on 64-bit and 181 on 32-bit, instead of the
> intended minimum of 1.
> 
> [...]

Applied, thanks!

[1/1] phy: freescale: phy-fsl-imx8-mipi-dphy: Fix hs_zero underflow
      commit: 9a0dd2a09484e5ba45eb8e6ab58c0effe18703a3

Best regards,
-- 
~Vinod