Re: [PATCH v3 03/10] dt-bindings: iio: frequency: add adi,ad9910-axi-backend

[Rob Herring (Arm)]

On Tue, 03 Nov 2026 11:52:59 -0300, Rodrigo Alencar wrote:
> Add bindings for the AD9910 AXI backend IP core. The FPGA IP core
> interfaces with the data and control pins of the AD9910 DDS, streaming
> data from memory via DMA into the 18-bit parallel data port (F[1:0] and
> D[15:0] pins), which is clocked by the PDCLK output of the device. It
> also drives the PROFILE[2:0] pins and the DRCTL pin, which controls the
> slope direction of the digital ramp generator (DRG). The DRCTL pin is
> driven by a PWM generator, so the IP core is described both as an IIO
> backend and as a PWM provider.
> 
> Signed-off-by: Rodrigo Alencar <rodrigo.alencar@xxxxxxxxxx>
> ---
>  .../iio/frequency/adi,ad9910-axi-backend.yaml      | 74 ++++++++++++++++++++++
>  MAINTAINERS                                        |  1 +
>  2 files changed, 75 insertions(+)
> 

Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>