[PATCH RFC 01/23] dt-bindings: clock: qcom: add SM8650 LPASS core & audio clock controllers
From: Neil Armstrong
Date: Fri Nov 13 2026 - 15:29:14 EST
The SM8650 LPASS HM, core, audio and AON clock controllers need to be
described to drive audio from Linux without the ADSP firmware.
Document these clock controllers and add their clock & power domain ids.
Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
---
.../bindings/clock/qcom,sm8650-lpasscorecc.yaml | 179 +++++++++++++++++++++
.../dt-bindings/clock/qcom,lpassaudiocc-sm8650.h | 47 ++++++
.../dt-bindings/clock/qcom,lpasscorecc-sm8650.h | 30 ++++
3 files changed, 256 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8650-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8650-lpasscorecc.yaml
new file mode 100644
index 000000000000..9c5207ee02f1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8650-lpasscorecc.yaml
@@ -0,0 +1,179 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm8650-lpasscorecc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm LPASS Core & Audio Clock Controllers on SM8650
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@xxxxxxxxxx>
+
+description: |
+ Qualcomm LPASS HM, core, audio and AON clock controllers provide the clocks
+ and power domains of the Low Power Audio SubSystem (LPASS) on SM8650, used
+ when LPASS is driven by Linux instead of the ADSP firmware.
+
+ See also:
+ include/dt-bindings/clock/qcom,lpasscorecc-sm8650.h
+ include/dt-bindings/clock/qcom,lpassaudiocc-sm8650.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,sm8650-lpassaoncc
+ - qcom,sm8650-lpassaudiocc
+ - qcom,sm8650-lpasscorecc
+ - qcom,sm8650-lpasshm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+
+ power-domains:
+ maxItems: 1
+
+ required-opps:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,sm8650-lpasshm
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Board XO source
+ clock-names:
+ items:
+ - const: bi_tcxo
+ required:
+ - power-domains
+ - '#power-domain-cells'
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,sm8650-lpasscorecc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Board XO source
+ clock-names:
+ items:
+ - const: bi_tcxo
+ required-opps: false
+ required:
+ - power-domains
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,sm8650-lpassaoncc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Board XO source
+ - description: LPASS_CORE_CC_CORE_CLK
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: iface
+ power-domains: false
+ required-opps: false
+ required:
+ - '#power-domain-cells'
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,sm8650-lpassaudiocc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Board XO source
+ - description: LPASS_AON_CC_MAIN_RCG_CLK_SRC
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: iface
+ required-opps: false
+ required:
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,lpassaudiocc-sm8650.h>
+ #include <dt-bindings/clock/qcom,lpasscorecc-sm8650.h>
+ #include <dt-bindings/clock/qcom,sm8650-gcc.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ clock-controller@6bc0000 {
+ compatible = "qcom,sm8650-lpassaudiocc";
+ reg = <0x06bc0000 0x38000>;
+ clocks = <&bi_tcxo_div2>;
+ clock-names = "bi_tcxo";
+ power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
+ #clock-cells = <1>;
+ };
+
+ lpass_aon: clock-controller@6e00000 {
+ compatible = "qcom,sm8650-lpassaoncc";
+ reg = <0x06e00000 0x30000>;
+ clocks = <&bi_tcxo_div2>, <&lpass_core LPASS_CORE_CC_CORE_CLK>;
+ clock-names = "bi_tcxo", "iface";
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ lpass_core: clock-controller@7b00000 {
+ compatible = "qcom,sm8650-lpasscorecc";
+ reg = <0x07b00000 0x58000>;
+ clocks = <&bi_tcxo_div2>;
+ clock-names = "bi_tcxo";
+ power-domains = <&lpass_hm LPASS_CORE_HM_GDSC>;
+ #clock-cells = <1>;
+ };
+
+ lpass_hm: clock-controller@7e00000 {
+ compatible = "qcom,sm8650-lpasshm";
+ reg = <0x07e00000 0xa000>;
+ clocks = <&bi_tcxo_div2>, <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>;
+ clock-names = "bi_tcxo", "iface";
+ power-domains = <&rpmhpd RPMHPD_LCX>;
+ required-opps = <&rpmhpd_opp_nom>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,lpassaudiocc-sm8650.h b/include/dt-bindings/clock/qcom,lpassaudiocc-sm8650.h
new file mode 100644
index 000000000000..c10e2a2639f1
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,lpassaudiocc-sm8650.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SM8650_H
+#define _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SM8650_H
+
+/* LPASS_AUDIO_CC clocks */
+#define LPASS_AUDIO_CC_CODEC_MEM_CLK 1
+#define LPASS_AUDIO_CC_CODEC_MEM0_CLK 2
+#define LPASS_AUDIO_CC_CODEC_MEM1_CLK 3
+#define LPASS_AUDIO_CC_CODEC_MEM2_CLK 4
+#define LPASS_AUDIO_CC_CODEC_MEM3_CLK 5
+#define LPASS_AUDIO_CC_RX_MCLK_CLK 6
+#define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC 7
+#define LPASS_AUDIO_CC_TX_MCLK_RX_CLK 8
+#define LPASS_AUDIO_CC_WSA_MCLK_CLK_SRC 9
+#define LPASS_AUDIO_CC_WSA_MCLK_CLK 10
+#define LPASS_AUDIO_CC_WSA2_MCLK_CLK 11
+#define LPASS_AUDIO_CC_TX_MCLK_WSA_CLK 12
+#define LPASS_AUDIO_CC_TX_MCLK_WSA2_CLK 13
+#define LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC 16
+#define LPASS_AUDIO_CC_CDIV_WSA_MCLK_DIV_CLK_SRC 17
+#define LPASS_AUDIO_CC_EXT_IF1_CLK_SRC 18
+#define LPASS_AUDIO_CC_EXT_IF1_IBIT_CLK 19
+#define LPASS_AUDIO_CC_EXT_IF2_CLK_SRC 20
+#define LPASS_AUDIO_CC_EXT_IF2_IBIT_CLK 21
+#define LPASS_AUDIO_CC_EXT_IF4_CLK_SRC 22
+#define LPASS_AUDIO_CC_EXT_IF4_IBIT_CLK 23
+#define LPASS_AUDIO_CC_EXT_IF5_CLK_SRC 24
+#define LPASS_AUDIO_CC_EXT_IF5_IBIT_CLK 25
+
+/* LPASS_AON_CC clocks */
+#define LPASS_AON_CC_MAIN_RCG_CLK_SRC 1
+#define LPASS_AON_CC_AUDIO_HM_H_CLK 2
+#define LPASS_AON_CC_TX_MCLK_CLK_SRC 3
+#define LPASS_AON_CC_TX_MCLK_CLK 4
+#define LPASS_AON_CC_VA_MEM0_CLK 5
+#define LPASS_AON_CC_CDIV_TX_MCLK_DIV_CLK_SRC 6
+#define LPASS_AON_CC_EXT_IF1_CLK_SRC 7
+#define LPASS_AON_CC_EXT_IF1_IBIT_CLK 8
+
+/* LPASS_AON_CC power domains */
+#define LPASS_AON_CC_LPASS_AUDIO_HM_GDSC 0
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,lpasscorecc-sm8650.h b/include/dt-bindings/clock/qcom,lpasscorecc-sm8650.h
new file mode 100644
index 000000000000..2849729a2e56
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,lpasscorecc-sm8650.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SM8650_H
+#define _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SM8650_H
+
+/* LPASS_CORE_CC clocks */
+#define LPASS_CORE_CC_DIG_PLL 0
+#define LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC 1
+#define LPASS_CORE_CC_DIG_PLL_OUT_ODD 2
+#define LPASS_CORE_CC_CORE_CLK 3
+#define LPASS_CORE_CC_CORE_CLK_SRC 4
+#define LPASS_CORE_CC_EXT_IF0_CLK_SRC 5
+#define LPASS_CORE_CC_EXT_IF0_IBIT_CLK 6
+#define LPASS_CORE_CC_EXT_IF1_CLK_SRC 7
+#define LPASS_CORE_CC_EXT_IF1_IBIT_CLK 8
+#define LPASS_CORE_CC_EXT_IF2_CLK_SRC 9
+#define LPASS_CORE_CC_EXT_IF2_IBIT_CLK 10
+#define LPASS_CORE_CC_LPM_CORE_CLK 11
+#define LPASS_CORE_CC_LPM_MEM0_CORE_CLK 12
+#define LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK 13
+#define LPASS_CORE_CC_EXT_MCLK0_CLK 14
+#define LPASS_CORE_CC_EXT_MCLK0_CLK_SRC 15
+
+/* LPASS Core power domains */
+#define LPASS_CORE_HM_GDSC 0
+
+#endif
--
2.34.1