Re: [PATCH v2] riscv: dts: spacemit: k1: give each PCIe port its own DMA window

[Yixun Lan]

Hi Vlad Banea,

On 21:31 Thu 12 Nov     , Vlad Banea wrote:
> On K1 a PCIe master only sees DDR: bus addresses 0-2 GB map to CPU
> 0-2 GB and bus 2-16 GB to CPU 4-18 GB. A root port does not forward
> upstream an inbound access that falls inside its own memory window, so
> dma-ranges must skip each port's own outbound window; the other ports'
> windows reach memory.
> 
> The shared pcie-bus skips all three windows, bus 0x8000_0000-0xb7ff_ffff,
> which leaves CPU addresses 0x1_0000_0000-0x1_37ff_ffff unreachable from
> every port. Give each port its own bus that skips only its own window.
> On boards with more than 2 GB of RAM, each port can then reach another
> 512-640 MB without SWIOTLB bouncing.
> 
> Signed-off-by: Vlad Banea <montrealtango@xxxxxxxxx>
> ---
> 
> Notes:
>     Changes in v2:
>     - describe the K1 PCIe address map instead of citing the vendor DT (Troy)
>     - "more than 2 GB" instead of 4 GB (Troy)
>     - drop the RFC tag
>     - RFC: https://lore.kernel.org/all/20261112015148.3911178-1-montrealtango@xxxxxxxxx/
>     
>     Tested on an OrangePi R2S (8 GB, RTL8125B on pcie1 and pcie2): SWIOTLB
>     use under load went from up to 87 slots to none.
> 
>  arch/riscv/boot/dts/spacemit/k1.dtsi | 27 +++++++++++++++++++++++++--
>  1 file changed, 25 insertions(+), 2 deletions(-)
> 
Reviewed-by: Yixun Lan <dlan@xxxxxxxxxx>

-- 
Yixun Lan (dlan)