[PATCH v1] coresight: etm4x: Fix instruction event 0 enablement

[Chao Xu]

According to section 7.3.30 of the Arm ETMv4 architecture specification,
TRCEVENTCTL1R.INSTEN[n] controls event n.

event_instren_store() uses TRCEVENTCTL1R_INSTEN_1 when TRCIDR0.NUMEVENT
is zero. For an ETM implementing only event 0, INSTEN[1] is RES0, so
writing event_instren cannot enable event 0 and no instruction Event
element is generated for it.

Use INSTEN[0] for the single-event case and update the comment accordingly.

Signed-off-by: Chao Xu <xuchao066@xxxxxxx>
---
 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index db9e603f97ba..420403dc711d 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -566,16 +566,16 @@ static ssize_t event_instren_store(struct device *dev,
 	sysfs_config->eventctrl1 &= ~TRCEVENTCTL1R_INSTEN_MASK;
 	switch (caps->nr_event) {
 	case 0x0:
-		/* generate Event element for event 1 */
-		sysfs_config->eventctrl1 |= val & TRCEVENTCTL1R_INSTEN_1;
+		/* generate Event element for event 0 */
+		sysfs_config->eventctrl1 |= val & TRCEVENTCTL1R_INSTEN_0;
 		break;
 	case 0x1:
-		/* generate Event element for event 1 and 2 */
+		/* generate Event element for event 0 and 1 */
 		sysfs_config->eventctrl1 |= val & (TRCEVENTCTL1R_INSTEN_0 |
 						   TRCEVENTCTL1R_INSTEN_1);
 		break;
 	case 0x2:
-		/* generate Event element for event 1, 2 and 3 */
+		/* generate Event element for event 0, 1 and 2 */
 		sysfs_config->eventctrl1 |= val & (TRCEVENTCTL1R_INSTEN_0 |
 					     TRCEVENTCTL1R_INSTEN_1 |
 					     TRCEVENTCTL1R_INSTEN_2);
-- 
2.43.0