Re: [PATCH v7 1/1] RISC-V: Add common csr_read_num() and csr_write_num() functions

[Anup Patel]

On Wed, Nov 11, 2026 at 5:16 PM Zhanpeng Zhang
<zhangzhanpeng.jasper@xxxxxxxxxxxxx> wrote:
>
> Hi Anup,
>
> On 11/5/26 12:15 AM, Anup Patel wrote:
> > From: Anup Patel <apatel@xxxxxxxxxxxxxxxx>
> >
> > In RISC-V, there is no CSR read/write instruction which takes CSR
> > number via register so add common csr_read_num() and csr_write_num()
> > functions which allow accessing certain CSRs by passing CSR number
> > as parameter. These common functions will be first used by the
> > ACPI CPPC driver and RISC-V PMU driver.
> >
> > Also, the RISC-V ACPI FFH specification allows arbitrary CSR number
> > as CPPC register and the RISC-V SBI specification allows arbitrary
> > CSR number as PMU hardware counter. This means ACPI CPPC driver and
> > RISC-V PMU driver no longer need to do sanity checks on CSR number
> > which are now done by the common csr_read_num() and csr_write_num()
> > functions.
> >
> > Signed-off-by: Anup Patel <apatel@xxxxxxxxxxxxxxxx>
> > Reviewed-by: Sunil V L <sunilvl@xxxxxxxxxxxxxxxx>
> > Reviewed-by: Andrew Jones <ajones@xxxxxxxxxxxxxxxx>
> > Reviewed-by: Atish Patra <atishp@xxxxxxxxxxxx>
> > Reviewed-by: Nutty Liu <nutty.liu@xxxxxxxxxxx>
> > ---
> >   arch/riscv/include/asm/csr.h |   3 +
> >   arch/riscv/kernel/Makefile   |   1 +
> >   arch/riscv/kernel/csr.c      | 165 +++++++++++++++++++++++++++++++++++
> >   drivers/acpi/riscv/cppc.c    |  17 ++--
> >   drivers/perf/riscv_pmu.c     |  54 ++----------
> >   5 files changed, 184 insertions(+), 56 deletions(-)
> >   create mode 100644 arch/riscv/kernel/csr.c
> >
> > [...]
> > +     switch (csr_num) {
> > +     switchcase_csr_read_32(CSR_CYCLE);
> > +     switchcase_csr_read_32(CSR_CYCLEH);
>
> Could we guard the CYCLEH cases with CONFIG_32BIT? They're RV32-only.

Okay, I will add #if for CONFIG_32BIT.

Regards,
Anup