> Greetings
>
> The problem is that the ISA bus architecture uses edge-triggered interrupts.
> That means that the processor only takes notice when the IRQ line drops from
> the 1 state to the 0 state, not if it is held low. Since the serial device only
> releases the IRQ line when the processor reads the latched data, no other
> negative transitions (i.e. interrupts) are possible in the meantime. This
> causes overrun errors in other devices hanging off the same IRQ line as
> their interrupts are not serviced in time (or at all actually).
But this doesn't explain why the IRQ3 ISR, for example, doesn't drain
both the COM1 and COM3 FIFOs *whenever it is invoked*. (I may have got
the IRQ wrong -- sorry.) If you can't tell which device invoked a shared
interrupt, you try to service them all.
Mark H. Wood, Lead System Programmer MWOOD@INDYVAX.IUPUI.EDU
Those who will not learn from history are doomed to reimplement it.