Ah, disabling the L1 cache would explain the slow down (this option
should disappear in future - the "L1 cache problem" appears to have
been overrated). It would also stress your L2 cache somewhat more
too - which could exercise motherboard problems due to poor signal
quality (the L1 cache problem was, allegedly, down to a non-Cyrix
approved, poor quality motherboard - maybe...).
The other likely looking possibility is allowing the branch table
to cache far branches (which I've only seen documented by IBM, not
Cyrix - although it appears to work fine on a 1 rev6 chip). You can
comment out the code that enables this in arch/i386/head.S by putting
an "#if 0" just before the bit that enables the debug registers and
an"#endif" just before the "sti" further down.
Mike
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