1. The scheme in .35 for SMP allows multiple ISRs to run in
different processors and synchronizes only on a cli. A cli
only completes when the cli-ing processor has locked further
ISR invocations and has waited until no other processors are in
irq code.
Question : Why is it not enough to just make sure that no
other processor is in cli-mode? We already allow
more than one ISR to be active without CLI.
2. There was a previous discussion about whether interrupts needed
to be disabled in the controller. Someone said that level triggered
devices would cause lock-up unless this were done.
Question: Is this correct?
Question: What devices need to be level triggered and why?