> Date: Tue, 14 Oct 1997 08:29:43 -0400 (EDT)
> From: "Richard B. Johnson" <root@chaos.analogic.com>
>
> I'd be willing to bet a dime that the PIO problem is a write-behind cache
> problem that is being masked by turning off interrupts during PIO
> operation, I'll bet that changing write-back to write-through "fixes"
> the problem.
>
> Can you say more.... ?
>
> - Ted
I no longer have a broken motherboad/CPU combination, but with a Cyrix
`486 on some clone motherboard I discovered a similar problem. Since I
have a logic analyzer here at work, I spent some time figuring out what
was happening. The motherboard had the capability of changing from
write-through caching to write-back caching and the board had been set
to the non-default write-back caching. When I set it to write-through
the problem went away.
The logic analyzer showed that when performing a sequence like `rep
outsw`, which performs a memory-read, followed by a port-write, the
cache controller would write data to the data bus when an I/O (port)
transfer was in progress, destroying existing data. When I turned off
write-back caching, the problem went away.
Cheers,
DJ
Richard B. Johnson
Analogic Corporation
Penguin : Linux version 2.1.55 on an i586 machine (66.15 BogoMips).
Warning : It's hard to stay on the trailing edge of technology.
Linux : Engineering tool
Spam : sync@localhost, daemon@loghost