> The IDT points to the end of a page such that vector 0x0E (page fault)
> is the start of the next page. The page with vectors 0-0xD is missing.
> This will cause all traps to cause a page fault. One assumes the page
> fault handler then fixes them up and handles them
Could someone explain what's going on for the benefit of those who slept
through their Processor Architecture course?
If I understand it right, the processor makes a half-hearted attempt to raise
an invalid opcode exception. If the vector for that is in memory but not the
cache, it'll crash and burn.
The workarounds that we've seen involve either locking the vector into the
cache so it generates the exception normally, or taking the vector out of
physical memory altogether so that a page fault is generated, from which we can clean up?
-- ---- ---- ---- David Woodhouse, Robinson College, CB3 9AN, England. (+44) 0976 658355 dwmw2@cam.ac.uk http://dwmw2.robinson.cam.ac.uk finger pgp@dwmw2.robinson.cam.ac.uk for PGP key.