Thank you for your prompt analysis of the beta fix. I'm
curious, though, why the page fault can break the bus lock, when the
(uncached) invalid operation exception couldn't. Optimistically, I'd
suppose that there's some fundamental difference in the implementation
of the page fault hardware path. Pessimisticly, though, there's the
possibility that the fix works only because the page fault handler is
executed relatively frequently (in the test systems), and a critical
gateway is always present in the L1 cache.
Would someone with a good knowledge of Pentium exception handling
and cache structures care to expand upon the analysis of the bug fix?
Craig Milo Rogers