> > Even with the fix, the PTE for the first page of the IDT has to be in
> > the TLB, otherwise we're right back in the same boat, right? (i.e. the
> > CPU would have to read the PTE from memory...)
>
> Wrong, the PTE corresponding to the first 7 entries of the IDT is marked
> invalid. And therefore it is never loaded in the TLB, which only caches
> valid entries by definition.
true that it's never loaded into the TLB, but the CPU has to 'load the PTE
from memory'.
> Note that according to Intel doc, descriptor table accesses are not
> locked. Locked descriptor and page table accesses are only performed when
> the processor realizes that it must update bits (such as accessed) in a
> table entry.
hm, maybe this explains why running another invalid instruction before the
F0 0F C7 C8 instruction 'fixes' the bug? After bootup, trap 6 should have
a cleared 'accessed' bit, correct?
-- mingo