Re: 2.1.63 - testing Pentium bug workaround..

Gabriel Paubert (paubert@iram.es)
Thu, 13 Nov 1997 22:42:42 +0100 (MET)


> >hm, maybe this explains why running another invalid instruction before the
> >F0 0F C7 C8 instruction 'fixes' the bug? After bootup, trap 6 should have
> >a cleared 'accessed' bit, correct?
>
> Hmmm, would it be possible to preset the "accessed" bit in the
> table entry as an alternative workaround?
>

Nope, the descriptors in the IDT, which must be either interrupt, trap or
task gates do not have an accessed bit. Only the memory segment descriptors
do have an accessed bit, which are essentially useless in a flat memory
model in which you typically have 4 segments which are set once for all

The task state segment descriptors also have a busy bit which is
automatically handled by the processor.

Gabriel.