There's a description of the ECP registers at
http://www.senet.com.au/~cpeacock/parallel.htm.
On the two motherboards I'm familiar with, the motherboard BIOS is
apparently responsible for setting up that value. In both cases,
it doesn't.
Those bits of the configB register are read only, but there's another
register in the super I/O chip which is read/write and controls that
value. There is another, different, register which tells which IRQ to
actually use.
The super I/O chip itself might be wired up funny -- e.g. on my motherboard
the DRQ3 pin is connected to the real DRQ1 line and the DRQ1,2 pins are
not connected. So the bios would have to configure the chip to use dma3
and state that it's using dma1. This is possible, but the bios does not
do anything of the kind, it's just all left with default settings.
(There's a Mickeysoft spec out there somewhere giving the canonical
definition of an ECP port, and the rationale and how-to-do-it stuff.
Unfortunatley I can't find the bookmark. If you want a fun time,
spend an afternoon writing a driver for it -- if you don't find three
unfixable race conditions in the first half hour you're not trying.)