Re: Question about the PCI bus.

Gabriel Paubert (paubert@iram.es)
Tue, 3 Feb 1998 11:30:40 +0100 (MET)


On Tue, 3 Feb 1998 bwoodard@cisco.com wrote:

> A friend of mine got a Toshiba 520 CDT laptop and we loaded rh5.0
> linux on it but the PCI chipset doesn't appear to be supported by
> Linux 2.1.84 yet. I have no problems with the pci chipset in my
> Toshiba 510 CDT. I was wondering where I could find some information
> about PCI as a reference. I don't know what is supposed to happen when
> the PCI bus driver probes the hardware. The error that is reported in
> the startup messages is:
>
> PCI: 00:10 [1179/060a/060700] has unknown header type 82, ignoring.
> PCI: 00:11 [1179/060a/060700] has unknown header type 82, ignoring.
>
> pci.c 92: pcibios_read_config_dwordbi(bus->number, devfn, PCI_VENDOR_ID, &l);
>

Up to now only PCI header types 0 and 1 were known to the kernel. However
PCI header type 2 does exist but its specification is well hidden.
I finally found it in Ralf Brown's interrupt list and immediately
forwarded my findings to Martin Mares, which is working on improving the
PCI handling code. Expect patches soon.

In the meantime, I include an excerpt from the description of PCI header
type 2 FYI (and for everybody's, I probably should have cc'ed it
to linux-kernel when I found it):

---header type 02h---
10h DWORD CardBus Socket/ExCa base address (see #0810)
bits 31-12: start address of socket interface register block
in 4K blocks
bits 11-0: reserved (0)
14h BYTE offset of capabilities list within configuration space(R/O)
(only valid if status register bit 4 set) (see #0804)
15h BYTE reserved
16h WORD secondary status
18h BYTE PCI bus number
19h BYTE CardBus bus number
1Ah BYTE subordinate bus number
1Bh BYTE CardBus latency timer
1Ch DWORD memory base address 0
20h DWORD memory limit 0
24h DWORD memory base address 1
28h DWORD memory limit 1
2Ch WORD I/O base address 0
2Eh WORD I/O base address 0 high word (optional)
30h WORD I/O limit 0
32h WORD I/O limit 0 high word (optional)
34h WORD I/O base address 1
36h WORD I/O base address 1 high word (optional)
38h WORD I/O limit 1
3Ah WORD I/O limit 1 high word (optional)
3Ch BYTE interrupt line
3Dh BYTE interrupt pin (read-only) (no interrupt used if 00h)
3Eh WORD bridge control
40h WORD subsystem vendor ID
42h WORD subsystem device ID
44h DWORD 16-bit PC Card legacy mode base address (for accessing ExCa
registers)
48h 14 DWORDs reserved
80h 32 DWORDs varies by device (see #0821,#0822,#0851,#0879)

> is the line that seems to generate the error. I traced it into
> arch/i386/kernel/bios32.c but I didn't know what access_pci is set to
> in this system. So without having to buy and read all the pci manuals
> can anyone give me some pointers on what I can do to troubleshoot this
> problem.
>
> The thing is that the hard disk and the cdrom and the video seem to be
> working fine. However, it seems as though this error might be be
> affecting the pcmcia services because they don't start up properly. (I
> haven't begun troubleshooting this yet) but something called ide1 is
> sitting on irq 15 on his 520 where the i82365 pcmcia controller lives
> on my 510.

Probably because PCI type header 2 is designed for PCI to CardBus (PCMCIA)
bridges. But I don't know anything about the pcmcia services.

Gabriel.