> Unless the (AC) Alignment Check bit is enabled in which case a misaligned
> access will indeed cause a trap.
>
No this is artificial and has nothing to do with bus errors. This
"feature" is available only in user mode (CPL 3). You set the AM
bit in CR0 and when the AC flag is set a trap to interrupt 17 will
occur.
This allows a user to attempt to optimize a program. Such "features"
can't be enabled in kernel-mode. Unaligned access just makes things
slow.... From the Intel Bible.. "Alignment check faults are generated
only in user mode (privilege level 3). Memory references which default
to privilige level 0, such as segment descriptor loads, do not generate
alignment-check faults, even when caused by a memory reference made in
user mode."
Cheers,
Dick Johnson
***** FILE SYSTEM MODIFIED *****
Penguin : Linux version 2.1.85 on an i586 machine (66.15 BogoMips).
Warning : It's hard to remain at the trailing edge of technology.
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