Re: TLB entries > 4kb

J.D. Bakker (bakker@thorgal.et.tudelft.nl)
Thu, 12 Feb 1998 23:05:11 +0100

>r> Has anybody ever looked into implementing that? What architectures besides
>r> MIPS could take advantage of such a feature?
>
>The MPC860. We now have 8 MByte Page Table entries for the Kernel Address
>Space and the Dual Ported RAM used to communicate with the CPM.

...and the IBM PPC403GC/GCX. Variable page sizes between 1k and 16M (in
eight steps, variable per TLB IIRC). This MMU, "designed for embedded apps"
according to IBM, also handles the process ID per TLB that Ralf mentioned
on the MIPS.

JDB (hunting for round tuits for that PPC board design)

Jan-Derk Bakker
Official Usenet Net.scum; see http://www.netscum.net

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