I believe the original poster was discussing multi-processor "shared
memory" (also called "reflected" memory) hardware systems, where the shared
memory (usually on a peripheral card for PCs) is multi-ported via a
high-speed serial/parallel bus and has a "back-door" port from one system
to another which is not controlled / controllable by the mobo chipset.
See, for example, Systran's SCRAMnet series at :
<http://www.systran.com/scramnet.htm>
In such a system, the mobo chipset memory controller isn't integrated with
the shared memory, and a remote system can write to a local shared memory
location without the local system's chipset / CPU being notified,
invalidating the local / CPU cache without notifying the local system of
the fact. In RTOSs which allow for such a setup, you can tell the OS that
a block of memory is to be locked down (not pageable) and not cached, so
that the CPU / chipset is always forced to fetch data directly from the
shared memory rather than from cache.
---------------------------------------------
Alex P. Madarasz, Jr. -- madarasz@erols.com
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