> VIA Chipsets should run two test.......since the addition of timing
> tuning feature that must be set at compile time.
Works well for me:
ide0: VP_IDE Bus-Master DMA Timing Config Success
ide1: BM-DMA at 0xfff8-0xffff, BIOS settings: hdc:pio, hdd:pio
ide1: VP_IDE Bus-Master DMA Timing Config Success
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
This is a VIA Apollo chipset:
00:07.1 IDE interface: VIA Technologies, Inc. VT82C586 IDE [Apollo] (rev 06)
LLaP
bero
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