o The data and clock lines are wire-AND. Zeros win.
o Don't confuse the bus protocol with what is actually implemented in a
particular system.
o The bus protocol *does* support multiple masters, without "hanging" the
winning master. On the other hand, a particular implementation may not
allow multiple masters.
o Driving the clock line from more than one place simultaneously *is*
allowed (for example it is how a receiver slows down a transmitter).
Again, this protocol feature may not be implemented in a system.
Let this thread die, please.
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